Along with the increasing demand for the miniaturization in the semiconductor manufacturing, the package technology has been evolved from two-dimension (2D) to three-dimension (3D) wafer package, so as to further improve the density and performance of circuits in an integrated circuit devices.
In the 3D wafer package, a plurality of wafers are stacked. A through silicon via (TSV) is typically used to connect a wafer to another wafer. However, the typical way to form the TSV introduces defects into the wafers and need to be solved.